1. Field of the Invention
The invention relates to the field of integrated circuit devices. Specifically, the invention relates to efficient performance of floating-point rounding operations for multiple number representation formats using incrementers.
2. Description of Related Art
Real numbers are represented in computer systems as floating-point numbers in the form of a digit string including three components: a sign, an exponent indicating the magnitude of the number and a significand or mantissa indicating the value of the fractional portion of the number. Many floating-point numbers cannot be accurately represented using a finite number of digits. The accuracy of a particular representation and the range of numbers that can be represented thus depends on the total number of digits or data bits available for the representation, as well as the portion of the total number of bits which is dedicated to the exponent and that which is dedicated to the mantissa.
In many computer systems, various formats, also referred to as precisions, are provided to represent floating-point numbers. Different precisions vary not only in the total number of bits used to represent a floating-point number, but also in the number of bits or size of the field used to represent each the exponent and the mantissa. The ANSI/IEEE Standard 754--1985 for binary floating-point arithmetic sets forth standard floating-point formats including single, double, and double-extended (also referred to as extended) precisions, which are used in many computer systems. In order to provide the flexibility to represent a wide range of numbers while also providing for varying degrees of accuracy, many computer systems support execution of floating-point operations in multiple precision modes.
Execution of a floating-point operation, such as a floating-point add or floating-point multiply operation, may produce a result for which the mantissa cannot be accurately represented given the mantissa field size allocated for a particular precision. In this case, in order to represent the result in the desired format, the mantissa may need to be rounded before the final result of the floating-point operation is used by the processor.
IEEE Standard 754 sets forth four rounding operations or modes: round up, round down, truncate and round to the nearest even. Different logic is usually provided for each type of rounding operation. For numbers which are to be rounded up, in many computer systems a full adder is used in order to implement a rounding unit which can round mantissas of multiple precisions. Use of a full adder to perform rounding operations for multiple precision modes is inefficient both in terms of the time required to perform rounding operations and the amount of space which must be allocated to the rounding unit. Since the results of many floating-point operations are rounded before being written back or utilized by other operations, the efficiency of the rounding logic can be critical in determining floating-point execution performance. Further, efficient use of space in an integrated circuit is an important consideration in order to minimize both the size and cost of the end product. Thus, it is desirable to have a more efficient rounding unit to improve floating-point execution performance and reduce the amount of space required for rounding logic which is capable of rounding numbers up in accordance with multiple precisions as well as other number representation formats which may be produced by a floating-point operation.